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2021-09-17

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Author：Jack

Via is one of the important components of** multi-layer PCB circuit boards**, and the cost of drilling usually accounts for 30% to 40% of the cost of** PCB manufacturing**. Simply put, every hole on the **PCB** can be called a via.

1. Parasitic capacitance of vias

The via itself has a parasitic capacitance to the ground. If it is known that the diameter of the isolation hole on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the **PCB board **is T, and the dielectric constant of the board substrate is ε, the size of the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1) The parasitic capacitance of the via will cause the circuit to prolong the rise time of the signal and reduce the speed of the circuit. For example, for a **PCB** with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, then we can approximate the via using the above formula The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF, the rise time change caused by this part of the capacitance is: T10-90=2.2C(Z0/2)=2.2 x0.517x(55/2)=31.28ps. It can be seen from these values that although the effect of the rise delay caused by the parasitic capacitance of a single via is not obvious, if the via is used multiple times in the trace to switch between layers, the designer should still consider carefully.

Second, the parasitic inductance of the via

Similarly, there are parasitic capacitances along with vias. In the design of **high-speed digital circuits**, the damage caused by the parasitic inductance of the vias is often greater than the impact of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can simply calculate the approximate parasitic inductance of a via with the following formula: L=5.08h[ln(4h/d)+1] where L refers to the inductance of the via, h is the length of the via, and d is the center The diameter of the hole. It can be seen from the formula that the diameter of the via has a small influence on the inductance, and the length of the via has the greatest influence on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance can no longer be ignored when high-frequency currents pass. Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power plane and the ground plane, so that the parasitic inductance of the vias will increase exponentially.

3. Via design in **high-speed PCB**

Through the above analysis of the parasitic characteristics of vias, we can see that in **high-speed PCB design**, seemingly simple vias often bring great negative effects to** circuit design**. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following can be done in the design:

1. Considering both cost and signal quality, choose a reasonable size via. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.

2. The two formulas discussed above can be concluded that using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.

3. The power and ground pins should be drilled nearby, and the lead between the via and the pin should be as short as possible, because they will increase the inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance.

4. Try not to change the layers of the signal traces on the PCB board, that is, try not to use unnecessary vias.

5. Place some grounded vias near the vias of the signal layer to provide the nearest loop for the signal. It is even possible to place a large number of redundant ground vias on the** PCB board**. Of course, the design needs to be flexible. The via model discussed earlier is the case where there are pads on each layer. Sometimes, we can reduce or even remove the pads of some layers. Especially when the density of vias is very high, it may lead to the formation of a break groove that separates the loop in the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider placing the via on the copper layer. The pad size is reduced.